A phase interpolator is a circuit that generates one or more phase-shifted outputs from one or more phases of an input clock. For example, if the input clock is expressed as A sin(ωt), the phase interpolator generates A sin(ωt+θ) as an output, where θ can vary from 0 to 360 degrees. θ is generally a function [f(k)] of a control signal k and can be varied using the control signal.
An existing phase interpolator includes a current mode logic (CML) summer to perform weighted sum of different phases of the input clock to generate the phase shifted outputs. As weights of the different phases are varied, different phase shifted outputs are obtained. The weights can be varied using tail currents of the CML summer. However, the CML summer leads to high power consumption and is area inefficient. For example, to generate four phase shifted outputs eight CML summer stages, each CML summer stage having two CML transistors, are required. Also, parasitic capacitance is present at output of each CML summer stage leading to high power consumption during charging and discharging. Further, the CML summer stages result in destructive interference between phases and hence the phase shifted outputs are obtained with a lower swing than that required. Thus, differential to single ended converters are required for level shifting the phase shifted outputs with lower swing to desired swing. Use of the differential to single ended converters increases power, cost and area.